July 7, 2016 Medium-term Management Plan Briefing Q&A
It has been claimed that EUV will be introduced for mass production from 2017 or 2018. Even if EUV is commercialized, as miniaturization will advance due to the combination of EUV and multiple patterning, the etching and deposition processes will not greatly decrease.
We are assuming that the results of technology that is now being introduced will emerge at the 7nm to 5nm generation nodes. It is important to be able to control processes where deposition and etching occur simultaneously, and we believe that TEL has an advantage, as it has knowledge of both deposition and etching.
We do not think that market share will change much. ASMI possesses many ALD patents and peripheral technologies, but there are many alternative technologies. We are in a good cooperative relationship with ASMI.
What you should focus on is the market share in the HARC process*3 for DRAM and 3D NAND, where TEL’s strengths lie, and market share in the patterning process for logic and DRAM. As we have already obtained some development PORs*4, we think that results will be seen from next year.
Our share for all HARC processes, including three 3D NAND processes and the DRAM capacitor process is around 40%, and for interconnect/contact processes it is around 80%. In regard to the patterning process, conductor etching and oxide etching are mixed together, and we believe our share is around 15%. Going forward, we will focus on the HARC process and the patterning process.
If we assume that multi-level contact is 100, we believe that slit is around 100, channel is around 120, and contact pad (staircase) is around 120.
We think the four processes specific to 3D NAND will grow, and we will focus on growing market share for the three processes of multi-level contact, channel and slit.
For NAND, cost is important. Thus, even if a two-deck is used and the number of processes doubles, there will be no benefit. We believe we will be able to differentiate ourselves by proposing solutions that combine processes and by using one deck instead of two-deck.
It is claimed at present that the limit is generally an aspect ratio of around 40, and we are engaged in development based on a target of 100.
As reported in the news release by ASML, it seems that they aim to establish, together with HMI, a method to detect defects at an early stage and provide feedback to exposure systems.
As dry etching systems are used in the TFT array process*5 for both LCD panels and OLED panels, it is difficult to calculate the share for OLED panels only. Our share for all etching processes for FPD manufacturing is around 65%. We have higher share related to large substrates than for small and medium-size substrates, but we will expand our share for small and medium-size substrates by introducing PICPTM*6 etching systems.
Market share varies by region and customer. In particular, South Korean FPD equipment makers tend to have high market share among South Korean customers, so we are assuming that our share will not grow much this fiscal year. However, as we have significantly raised the performance of our PICPTM etching systems compared to previous systems, South Korean customers are also considering adopting them and we are hoping for growth here.
We are conducting design to suit the customer’s substrate size. In regard to organic materials, customers are at the stage of evaluating both high polymer and low polymer in terms of color, life, structure and cost. We are targeting mainly OLED TVs, and with regard to resolution, in the case of 55-inch 4K TVs, 80ppi (pixel per inch) should be sufficient. In the future, we will aim for a resolution of 130ppi, which will be necessary for 65-inch 8K TVs.
We should be able to resolve this sufficiently by reducing overall film thickness by painting RGB separately with inkjet printing systems.
There is great potential. We will promote business in an integrated way with customers and material makers to establish the inkjet process for OLED TVs.
ALD (Atomic Layer Deposition): An atomic level film deposition technique
ALE (Atomic Layer Etch): An atomic level etching technique
HARC (High Aspect Ratio Contact) process: Advanced processing technology required for deep hole etching
POR (Process of Record): Certification of the adoption of equipment in customers' semiconductor production processes
TFT Array process: Substrate formation process that realizes display images
PICP: Plasma source for producing extremely uniform high-density plasma on substrate
The above content is a summary of a question and answer session.
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